1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to the improvement of substrate bias generating circuits of semiconductor memory devices.
2. Description of the Background Art
FIG. 12 is a block diagram showing a conventional dynamic type semiconductor memory device containing an internal voltage down converting circuit (Voltage Down Converter) therein.
The semiconductor memory device includes a dynamic random access memory (hereinafter referred to as a DRAM) 100, an internal voltage down converting circuit 200 and a substrate bias generating circuit 300. The DRAM 100, the internal voltage down converting circuit 200 and the substrate bias generating circuit 300 are formed on a semiconductor substrate CH.
The semiconductor memory device is supplied with an external power supply voltage Vcc and a ground voltage Vss. The internal voltage down converting circuit 200 converts the external power supply voltage Vcc down to a predetermined internal power supply voltage IVcc to supply the same to the DRAM 100. The internal voltage down converting circuit 200 is provided to improve reliability by reducing electric fields applied to gate oxide films of transistors, and reduce current consumption.
In order to always retain the semiconductor substrate CH at a predetermined potential, the substrate bias generating circuit 300 generates a substrate bias V.sub.BB of the predetermined potential. The substrate bias generating circuit 300 is provided for the following purposes.
In the inside of a CMOS integrated circuit, a parasitic bipolar transistor is structurally constructed. When electrons are injected from a input terminal to, for example, a P type semiconductor substrate by undershoot of an input waveform, the parasitic bipolar transistor operates, and latch-up takes place. As a result, data stored in memory cells are destroyed. It is necessary to prevent such a destruction of data.
In addition, a pn junction capacitance is formed between the semiconductor substrate and each node of the internal circuitry. If the pn junction capacitance is large, the high speed operation of the circuitry is prevented. Therefore, it is necessary to reduce such a pn junction capacitance.
Moreover, a threshold voltage of an MOS transistor depends on a potential of the semiconductor substrate. It is called a body effect of the threshold voltage of the transistor. When the potential of the P type semiconductor substrate is relatively low, the threshold voltage of the N channel MOS transistor hardly changes though the potential of the semiconductor substrate changes. However, when the potential of the P type semiconductor substrate is relatively high, the threshold voltage of the N channel MOS transistor considerably changes according to the change of the potential of the semiconductor substrate. It is thus necessary to always retain the potential of the P type semiconductor substrate low.
The substrate bias generating circuit 300 is provided to prevent destruction of memory cell data, allow high speed circuit operation by reducing a pn junction capacitance, and allow high speed and stabilized circuit operation by reducing a body effect of a threshold voltage.
FIG. 13 is a circuit diagram showing a structure of a conventional substrate bias generating circuit. A substrate bias generating circuit is disclosed in, for example, Japanese Patent Laying-Open Nos. 1-223693, 1-255095, and 2-61890.
The substrate bias generating circuit 300 includes two V.sub.BB generating circuits 31, 32. The V.sub.BB generating circuit 31 includes inverters G11 to G14, and a NOR gate G15, a capacitor C1 and N channel MOS transistors N11, N12.
The inverters G11 to G14 are connected in series and the output terminal of the inverter G14 is connected to one input terminal of the NOR gate G15. The output of the NOR gate G15 is connected to the input terminal of the inverter G11. The inverters G11 to G14 and the NOR gate G15 constitute a ring oscillator.
The other input terminal of the NOR gate G15 is connected to an enable terminal BBE. The output terminal of the NOR gate G15 (node NA) is connected to one electrode of the capacitor C1, and the other electrode of the capacitor C1 is connected to a node NB. The transistor N11 is connected between the node NB and an output terminal TO supplying the substrate bias V.sub.BB, and the transistor N12 is connected between the node NB and a ground terminal. The enable terminal BBE is connected to the ground terminal.
The structure of the V.sub.BB generating circuit 32 is the same as that of the V.sub.BB generating circuit 31, except that a capacitor C2 included in the V.sub.BB generating circuit 32 has a larger capacitance value than that of the capacitor C1 included in the V.sub.BB generating circuit 31, and that the substrate bias V.sub.BB supplied from the output terminal TO of the V.sub.BB generating circuit 32 is applied to a level detector 33, and an enable terminal BBE is supplied with an output signal of the level detector 33.
FIG. 14 shows a structure of the inverter G11 included in the V.sub.BB generating circuits 31, 32. The inverter G11 includes a P channel MOS transistor P21 and an N channel MOS transistor N21. The transistor P21 is connected between a power supply terminal receiving the external power supply voltage Vcc and an output terminal b, and the transistor N21 is connected between the output terminal b and a ground terminal. The gates of the transistors P21, N21 are connected to an input terminal a. The structures of the inverters G12 to G14 are the same as that of the inverter G11.
FIG. 15 shows the structure of the NOR gate G15 included in the V.sub.BB generating circuits 31, 32. The NOR gate G15 includes P channel MOS transistors P31, P32 and N channel MOS transistors N31, N32. The transistors P31, P32 are connected in series between a power supply terminal receiving the external power supply voltage Vcc and an output terminal C. The transistors N31, N32 are connected in parallel between the output terminal C and a ground terminal. The gates of the transistors P32, N31 are connected to an input terminal A, and the gates of the transistors P31, N32 are connected to an input terminal B.
The inverters G11 to G14 and the NOR gate G15 of the V.sub.BB generating circuits 31, 32 are thus driven by the external power supply voltage Vcc.
Referring to a waveform diagram of FIG. 16, the operation of the V.sub.BB generating circuit 31 shown in FIG. 13 will now be described. In this figure, the threshold voltage of the transistors N11, N12 is Vth.
Since the enable terminal BBE of the V.sub.BB generating circuit 31 is connected to the ground terminal, the NOR gate G15 operates as an inverter. Consequently, the inverters G11 to G14 and the NOR gate G15 constitute a ring oscillator, and a potential of the node NA is a square wave changing repeatedly between the external power supply voltage Vcc and 0 V. By the operations of the capacitor C1 and the transistor N12, a potential of the node NB becomes a square wave changing repeatedly between the voltage Vth and the voltage Vth-Vcc. As a result, the substrate bias V.sub.BB at the 2 Vth-Vcc level is generated from the output terminal TO.
For example, when the external power supply voltage Vcc is 5 V, and the threshold voltage Vth of the transistors N11, N12 is 1 V, the substrate bias V.sub.BB is -3 V.
The V.sub.BB generating circuit 32 shown in FIG. 13 is activated in response to an output signal of the level detector 33.
The level detector 33 applies an output signal of "L" to the enable terminal BBE when the substrate bias V.sub.BB is higher than, for example, -2 V, whereby the V.sub.BB generating circuit 32 is activated. When the substrate bias V.sub.BB falls below -2 V, the level detector 33 applies an output signal of "H" to the enable terminal BBE, whereby the V.sub.BB generating circuit 32 is inactivated.
Briefly, both of the V.sub.BB generating circuit 31 having the small capacitor C1 and the V.sub.BB generating circuit 32 having the large capacitor C2 operate until the substrate bias V.sub.BB falls to -2 V, and when the substrate bias V.sub.BB becomes lower than -2 V, only the V.sub.BB generating circuit 31 having the small capacitor C1 operates. In the above described manner, the substrate bias V.sub.BB, for example -3 V, is applied to the semiconductor substrate CH shown in FIG. 12.
As described above, in the conventional semiconductor memory device shown in FIG. 12, the semiconductor substrate CH is always supplied with the substrate bias V.sub.BB by means of the substrate bias generating circuit 300 driven by the external power supply voltage Vcc. Consequently, a problem of large power consumption arises.